1. Field of the Invention
The present invention relates to shift register circuits applicable to scanning line driving circuits, and particularly to a shift register circuit applicable to a scanning line driving circuit used in an image display apparatus having a partial display function and formed only of field-effect transistors of a same conductivity type.
2. Description of the Background Art
In an image display apparatus (hereinafter referred to as “a display apparatus”) such as a liquid-crystal display apparatus, a gate line (scanning line) is provided for each pixel row (pixel line) on a display panel where a plurality of pixels are arranged in a matrix, and the gate lines are sequentially selected and driven in cycles of one horizontal period of a display signal to update the displayed image. For a gate line driving circuit (scanning line driving circuit) for sequentially selecting and driving the pixel lines or gate lines, a shift register that performs shift operation circulating in one frame period of the display signal can be used.
In the field of display apparatuses, techniques are known which reduce power consumption by making “partial display” by limiting the display to only a part of the screen. Specifically, the techniques disclosed in Japanese Patent Application Laid-Open Nos. 2008-140490 (hereinafter Patent Document 1) and 2008-58939 use shift registers formed only of field-effect transistors of the same conductivity type. When a shift register provided in a display apparatus is formed only of transistors of the same conductivity type, the number of process steps in the manufacturing process of the display apparatus can be reduced to reduce manufacturing costs.
A shift register as a gate line driving circuit is formed of a plurality of cascade-connected shift register circuits provided respectively for individual pixel lines or gate lines. In this specification, for the sake of convenience of description, each of the plurality of shift register circuits forming such a gate line driving circuit is referred to as “a unit shift register”. That is to say, an output signal of each unit shift register of a gate line driving circuit is supplied to a gate line, and also inputted to a unit shift register in a next or following stage.
For example, Patent Document 1 discloses a scanning line driving circuit applicable to partial display, and FIG. 3 thereof shows the circuit configuration of a unit shift register (Ua) forming it. The unit shift register (Ua) outputs a scanning signal (Y) for driving a scanning line and a transfer signal (G) sent to the unit shift register in the next stage. In the unit shift register (Ua), a transfer signal generator (110A) for generating the transfer signal (G) always operates, while a scanning signal generator (120A) for generating the scanning signal (Y) is controlled to operate only in selected periods of pixel lines required to make display in partial display (display effective periods).
The scanning signal generator (120A) includes a first transistor (121) connected between a first clock terminal (P) and a scanning signal output terminal (y). The transfer signal generator (110A) includes a second transistor (111) connected between a second clock terminal (A) and a transfer signal output terminal (g). The gates of the first and second transistors (121, 111) are connected to each other, and they switch on and off with the same timing.
Now, a second clock signal (YCK1/YCK2) inputted to the second clock terminal (A) of each unit shift register (Ua) is activated always in given cycles, but a first clock signal (P1/P2) inputted to the first clock terminal (P) is activated in given cycles only in display effective periods, and it is maintained at an inactive level in the remaining periods (display ineffective periods). Thus, the scanning signal (Y) is activated only in display effective periods. As a result, only part of the pixel lines are activated, and partial display on the screen is achieved.
In the unit shift register (Ua) of FIG. 3 of Patent Document 1, a capacitance element (113) is connected between the source (transfer signal output terminal (g)) and the gate of the second transistor (111). This capacitance element (113) steps up the gate of the second transistor (111) when the transfer signal (G) is activated, and thus serves to enhance the driving capability (the capability of passing current) of the second transistor (111). When the gate of the second transistor (111) is sufficiently stepped up, the second transistor (111) operates in a non-saturation region, and the potential of the active level of the transfer signal (G) becomes higher.
As stated above, the gates of the first and second transistors (121, 111) are connected to each other, so that the driving capability of the first transistor (121) is also enhanced when the gate of the second transistor (111) is stepped up. Here, a node (a) to which the gates of the first and second transistors (121, 111) connect is referred to as “a gate node”.
The first and second transistors (121, 111) each have gate capacitance (gate-source capacitance, gate-drain capacitance and gate-channel capacitance). In a display effective period, when the first and second transistors (121, 111) turn on, the transfer signal output terminal (g) and the scanning signal output terminal (y) are both charged in response to activation of the first clock signal (P1/P2) and second clock signal (YCK1/YCK2), and the gate capacitances of the first and second transistors (121, 111) both function to step up the gate node (a) together with the capacitance element (113).
However, in a display ineffective period, the second clock signal (YCK1/YCK2) is activated but the first clock signal (P1/P2) is not activated. Accordingly, when the first and second transistors (121, 111) turn on, only the transfer signal output terminal (g) is charged but the scanning signal output terminal (y) is not charged. In this case, the gate capacitance of the second transistor (111) functions to step up the gate node (a), but the gate capacitance of the first transistor (121) serves to hinder it. When the gate node (a) is insufficiently stepped up for this reason, the driving capability of the second transistor (111) of the unit shift register (Ua) is lowered in the display ineffective period. This hinders high-speed operation of the unit shift register (Ua), and lowers the operational margin of the scanning line driving circuit.
The first transistor (121) is required to have high driving capability to drive a gate line having large load capacitance, and its gate width is set wide. Accordingly, the gate capacitance of the first transistor (121) has a large value (the gate capacitance is proportional to the product of the gate width and gate length), and this problem is likely to occur.